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μ PD44647094A-A, 44647184A-A, 44647364A-A, 44647096A-A, 44647186A-A, 44647366A-A
2.5 Clock Cycles Read Latency
[ μ PD44647096A-A], [ μ PD44647186A-A], [ μ PD44647366A-A]
NOP
READ
WRITE
READ
WRITE
NOP
NOP
1
2
3
4
5
6
7
8
K
TKHKL
TKLKH
TKHKH
TKHK#H TK#HKH
K#
R#
T IVKH
TKHIX
TIVKH
TKHIX
W#
Address
A0
A1
A2
A3
TAVKH
TKHAX
TDVKH
TKHDX
TDVKH
TKHDX
Data in
D10
D11
D12
D13
D30
D31
D32
D33
ODT state
D, BW#
ODT-ON
QVLD
TCQHQVLD
TCQHQVLD
Read Latency = 2.5 clock cycles
TKHQV
TKHQV
TKHQX1
TKHQX
TKHQX
TKHQZ
Data out
Q00
Q01
Q02
Q03
Q20
Q21
Q22
Q23
TCQHQX
TCQHQX
CQ
TKHCQV
TKHCQX
TCQHQV
TCQHQV
TKHCQV
TCQHCQ#H
TCQ#HCQH
TKHCQX
CQ#
Remarks 1. Q00 refers to output from address A0+0.
Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.
2. Outputs are disabled (high impedance) 4.5 clock cycles after the last READ (R# = LOW) is input in the
sequences of [READ]-[NOP]-[NOP], [READ]-[WRITE]-[NOP] and [READ]-[NOP]-[WRITE].
3. In this example, if address A2 = A1, data Q20 = D10, Q21 = D11, Q22 = D12 and Q23 = D13.
Write data is forwarded immediately as read results. This remark applies to the whole diagram.
4. When the ODT control pin is LOW or No Connect, the ODT function is always off.
Data Sheet M19962EJ2V0DS
21
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